Developing a Fault-Tolerant Demand-Based Structure for 3D Wireless Networks on Chip Architecture

In Network-on-Chip architecture, wired structure and multi-step communication increase consumption power and latency. Combining wired media for a regular transmission and high-bandwidth wireless media for multi-step communication is a way to reduce latency and consumption of power. Wireless nodes are prone to error in on-chip wireless networks due to their complexity and relatively high usage; they are also crowded due to their sharing between several nodes, but their job is to increase efficiency. However, the presence of wireless nodes in wireless networks on the chip increases the cost and area. Therefore, finding an optimal structure for communication between cores is necessary. In this paper, a new three-dimensional architecture for a Wireless Network on Chip is presented, which has two levels; depending on the location of the error in the second level, the wireless routers in the first level are assigned to the processing elements. The demand matrix is used to optimize different traffic patterns. The performance of 3D architecture has been compared under different traffic patterns. The obtained results show that the proposed structure has a relatively good performance and increases the network's reliability